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gnucap:manual:tech:spice2verilog - hsp and uic

Porting/Converting Spice to Verilog(-AMS) Verilog-AMS has been designed to coexist with Spice, and to replace it as needed (among other things). Citing from Annex E of the language reference manual, Analog simulation has long been performed with SPICE and SPICE-like simulators. As such, there is a huge legacy of SPICE netlists. These are supposed to retain its use when upgrading a SPICE simulator. On the other hand, Annex E provides a list of “SPICE primitives” that facilitate the rewrite of ba…

gnucap:manual:languages:spice - spice update and reference verilog

SPICE has irregular and confusing syntax. The preferred way to use SPICE netlists is through subckt declarations. A subckt declaration creates a type that can be used in any language. Case sensitivity can be enabled (default is off in Spice), in order to avoid problems later, when the netlist is expanded.

gnucap:manual:languages:verilog - update

WARNING, TRANSITION In order to get the most up-to-date verilog experience, you should use the Verilog language implementation from modelgen-verilog. See “Status” below. END WARNING The Verilog language plugin attempts to support the syntax of the Verilog-AMS language.

gnucap:manual:tech:plugins:devices:allocation_and_setup - common comparison operators

Implementation Allocation and setup default constructor A default constructor is required. It is used to construct the static object that is registered with the dispatcher. It should do what a default constructor usually does. copy constructor A copy constructor is required. Most objects are created by the copy constructor, as copies of the object registered with the dispatcher. Usually, it should do a SHALLOW copy. In particular, a COMMON should be linked and not copied. A copy const…

gnucap:manual:tech:style - reference white and black space

This section provides guidelines for programmers. Some of them are arbitrary. Please follow them for consistency. If you prefer a different way, please consider that it would be much worse to deal with a dozen different ways in the same body of code.

gnucap:manual:tech:white_and_black_space - initial version

Neither white nor black space has any function, but it is used to arrange characters on the screen, and/or make your code easier to read. Such characters are space, tab and newline. Do not use carriage return or other fancy stuff. On this page, we summarise the most important rules. If there are violations in the code, they should be fixed when the code is edited. Ideally this happens for some other reason.

gnucap:start - related work elsewhere: link to docs at IHP

Gnucap is the GNU Circuit Analysis Package Gnucap is a modern post-spice circuit simulator with several advantages over Spice derivatives. Gnucap and Modelgen-Verilog support a reasonable subset of Verilog-A, for both structural and behavioural analog/mixed models. Work towards Verilog-AMS with NLnet funding is ongoing.

gnucap:user:netlist_import_and_export:qucs - [Qucs specific types] add parameters

Import and export: Qucs Verilog schematics There is work in progress to replace the Qucs file format for more transparency, versatility and data exchange based on Verilog. See for the current status.

gnucap:user:netlist_import_and_export:geda - [Parameter declarations] add example

The gEDA file format is well known and flexible. Today it is used in Lepton, which provides an editor similar to gschem. A gEDA schematic stores a circuit, and in the proposed format a circuit will be represented as a module. Using Verilog this gives us

gnucap:projects:interface_wrappers - created

Device Interface wrappers, work in progress and questions (c.f. here). * Could the gnucap verilog modelgen be made to target other simulators with enough work or is it very tightly coupled to gnucap internals throughout? For example something like OSDI to replace/supplement OpenVAF in ngspice/vacask?

gnucap:manual:commands:dc - update, parameter sweeps, mention pipe

Purpose Performs a nonlinear DC steady state analysis, and sweeps the signal input, a component value or a parameter value. Components must be of type “element”, such as voltage/current sources and resistors. Sweeping parameters that are used to control expansion (binning or generate) will not trigger re-expansion, and hence might lead to unexpected results.

gnucap:manual:modelgen-verilog - man page: copy in current version

See below for man page (as of Nov '25). The current version is available here. Relevant project page. Modelgen-verilog implementation notes are here. GNUCAP-MG-VAMS(1) Gnucap Modelgen GNUCAP-MG-VAMS(1) NAME gnucap-mg-vams - GNU Circuit Analysis Package .vams translator SYNOPSIS gnucap-mg-vams { [OPTIONS] [ACTIONS] } DESCRIPTION Gnucap-Modelgen is a translator tool in the Gnucap suite. It will trans‐ form Verilog-AMS models into C++ cod…

gnucap:manual:tech:modelgen-verilog - add storage types

The term “modelgen” refers to the device model generator and language that has been part of the Gnucap project from early on. Modelgen reads device descriptions and emits C++ code to be compiled into plugins. Support for Verilog-AMS compact models has been implemented in a modelgen successor, “modelgen-verilog”, following the design patterns and device architecture. Major technical advantages of the latter are automatic differentiation and support for device specific numerical tolerances. Others…